Hướng dẫn xử lý lỗi configuration item ald current threshold năm 2024

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arSố TTEnglishNháp 0Nháp 1Nháp 2 Nháp 3Nháp 4Nháp 5Nháp 6Nháp 7Nháp 8

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ar

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ar1Defines number of Microseconds software will wait before polling 'Link Training' bit in "Link Status" register. Value range from 10 to 1000 uS.Defines number of Microgiâyonds software will wait before polling 'Link Training' bit in Link Status register. Value range from 10 to 1000 uS.

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2Completion TimeoutCompletion Timeout

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3In device Functions that support Completion Timeout programmability, allows system software to modify the Completion Timeout value. 'Default' 50us to 50ms. If 'Shorter' is selected, software will use shorter timeout ranges supported by hardware. If 'Longer' is selected, software will use longer timeout ranges.In device Functions that support Completion Timeout programmability, allows system software to modify the Completion Timeout value. 'Default' 50us to 50ms. If 'Shorter' is selected, software will use shorter timeout ranges supported by hardware. If 'Longer' is selected, software will use longer timeout ranges.

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4DefaultDefaultMặc định

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5ARI ForwardingARI Forwarding

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6If supported by hardware and set to 'Enabled', the Downstream Port disables its traditional Device Number field being 0 enforcement when turning a Type1 Configuration Request into a Type0 Configuration Request, permitting access to Extended Functions in an ARI Device immediately below the Port. Default value: DisabledIf supported by hardware and set to 'Enabled', the Downstream Port disables its traditional Device Number field being 0 enforcement when turning a Type1 Configuration Request into a Type0 Configuration Request, permitting access to Extended Functions in an ARI Device immediately below the Port. Default value: Disabled

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7AtomicOp Requester EnableAtomicOp Requester Enable

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8If supported by hardware and set to 'Enabled', this function initiates AtomicOp Requests only if Bus Master Enable bit is in the Command Register Set.If supported by hardware and set to 'Enabled', this function initiates AtomicOp Requests only if Bus Master Enable bit is in the Command Register Set.

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9IDO Request EnableIDO Request Enable

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10If supported by hardware and set to 'Enabled', this permits setting the number of ID-Based Ordering (IDO) bit (Attribute[2]) requests to be initiated.If supported by hardware and set to 'Enabled', this permits setting the number of ID-Based Ordering (IDO) bit (Attribute[2]) requests to be initiated.

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11IDO Completion EnableIDO Completion Enable

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12If supported by hardware and set to 'Enabled', this permits setting the number of ID-Based Ordering (IDO) bit (Attribute[2]) requests to be initiated.If supported by hardware and set to 'Enabled', this permits setting the number of ID-Based Ordering (IDO) bit (Attribute[2]) requests to be initiated.

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13LTR Mechanism EnableLTR Mechanism Enable

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14If supported by hardware and set to 'Enabled', this enables the Latency Tolerance Reporting (LTR) Mechanism.If supported by hardware and set to 'Enabled', this enables the Latency Tolerance Reporting (LTR) Mechanism.

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15End-End TLP Prefix BlockingEnd-End TLP Prefix Blocking

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16If supported by hardware and set to 'Enabled', this function will block forwarding of TLPs containing End-End TLP Prefixes.If supported by hardware and set to 'Enabled', this function will block forwarding of TLPs containing End-End TLP Prefixes.

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17Target Link SpeedTarget Link Speed

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18If supported by hardware and set to 'Force to 2.5 GT/s' for Downstream Ports, this sets an upper limit on Link operational speed by restricting the values advertised by the Upstream component in its training sequences. When 'Auto' is selected HW initialized data will be used.If supported by hardware and set to 'Force to 2.5 GT/s' for Downstream Ports, this sets an upper limit on Link operational speed by restricting the values advertised by the Upstream component in its training sequences. When 'Auto' is selected HW initialized data will be used.

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19Force to 2.5 GT/sForce to 2.5 GT/sÉp tới tốc độ 2.5 GT/s

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20Force to 5.0 GT/sForce to 5.0 GT/sÉp tới tốc độ 5.0 GT/s

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21Compliance SOSCompliance SOS

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22If supported by hardware and set to 'Enabled', this will force LTSSM to send SKP Ordered Sets between sequences when sending Compliance Pattern or Modified Compliance Pattern.If supported by hardware and set to 'Enabled', this will force LTSSM to send SKP Ordered Sets between sequences when sending Compliance Pattern or Modified Compliance Pattern.

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23Hardware Autonomous WidthHardware Autonomous Width

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24If supported by hardware and set to 'Disabled', this will disable the hardware's ability to change link width except width size reduction for the purpose of correcting unstable link operation.If supported by hardware and set to 'Disabled', this will disable the hardware's ability to change link width except width size reduction for the purpose of correcting unstable link operation.

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25Hardware Autonomous SpeedHardware Autonomous Speed

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26If supported by hardware and set to 'Disabled', this will disable the hardware's ability to change link speed except speed rate reduction for the purpose of correcting unstable link operation.If supported by hardware and set to 'Disabled', this will disable the hardware's ability to change link speed except speed rate reduction for the purpose of correcting unstable link operation.

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27Clock Power ManagementClock Power Management

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28If supported by hardware and set to 'Enabled', the device is permitted to use CLKREQ# signal for power management of Link clock in accordance to protocol defined in appropriate form factor specification.If supported by hardware and set to 'Enabled', the device is permitted to use CLKREQ# signal for power management of Link clock in accordance to protocol defined in appropriate form factor specification.

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29ShorterShorter

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30LongerLonger

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31Unpopulated LinksUnpopulated Links

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32In order to save power, software will disable unpopulated PCI Express links, if this option set to 'Disable Link'.In order to save power, software will disable unpopulated PCI Express links, if this option set to 'Disable Link'.

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33Keep Link ONKeep Link ON

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34Disable LinkDisable Link

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35PCIE GEN3PCIE GEN3

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36PCIE 3.0PCIE 3.0

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37PCI Express GEN3 Support.PCI Express GEN3 Support.

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38Performance TuningPerformance Tuning

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39Performance Tuning ParametersPerformance Tuning Parameters

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40CPU ConfigurationCPU Configuration

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41North Bridge ConfigurationNorth Bridge ConfigurationCấu hình cầu bắc

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42South Bridge ConfigurationSouth Bridge ConfigurationCấu hình cầu nam

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43Non Turbo Ratio OverrideNon Turbo Ratio Override

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44Host Clock Override(1/100 MHz)Host Clock Override(1/100 MHz)

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45Host Clock OverrideHost Clock Override

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46Turbo ModeTurbo Mode

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47Enhanced Intel SpeedStep TechnologyEnhanced Intel SpeedStep Technology

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481 Core Ratio Limit1 Core Ratio Limit

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492 Core Ratio Limit2 Core Ratio Limit

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503 Core Ratio Limit3 Core Ratio Limit

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514 Core Ratio Limit4 Core Ratio Limit

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525 Core Ratio Limit5 Core Ratio Limit

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536 Core Ratio Limit6 Core Ratio Limit

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54Runtime Core Ratio LimitRuntime Core Ratio Limit

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55Runtime Core Ratio LimitRuntime Core Ratio Limit

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56IA Core Current Max(1/8 Amp)IA Core Current Max(1/8 Amp)

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57iGFX Core Current Max(1/8 Amp)iGFX Core Current Max(1/8 Amp)

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58Cpu Voltage (1/256)Cpu Voltage (1/256)

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59Power Limit 2 SwitchPower Limit 2 Switch

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60Power Limit 2 Value(1/8 Watt)Power Limit 2 Value(1/8 Watt)

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61Power Limit 1 Value(1/8 Watt)Power Limit 1 Value(1/8 Watt)

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62Reference RatioReference Ratio

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63Internal PLL OvervoltadgeInternal PLL Overvoltadge

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64Enable this function will caure the S3 resume failure.Enable this function will caure the S3 resume failure.

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65Runtime Turbo EnableRuntime Turbo Enable

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66North Bridge ConfigurationNorth Bridge Configuration

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67Memory Multiplier ConfigurationMemory Multiplier Configuration

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68Memory Timing ConfigurationMemory Timing Configuration

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69CAS# Latency(tCL)CAS# Latency(tCL)

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70Cas Latency, Range 3-15.Cas Latency, Range 3-15.

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71Row Precharge Time(tRP)Row Precharge Time(tRP)

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72Row Precharge Time, Range 3-15.Row Precharge Time, Range 3-15.

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73RAS# to CAS# Delay(tRCD)RAS# to CAS# Delay(tRCD)

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74Row Address to Column Address Delay, Range 3-15.Row Address to Column Address Delay, Range 3-15.

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75RAS# Active Time(tRAS)RAS# Active Time(tRAS)

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76Row Active Time, Range 9-63.Row Active Time, Range 9-63.

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77Write Recovery Time(tWR)Write Recovery Time(tWR)

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78Internal Write to Read Command Delay, Range 3-31.Internal Write to Read Command Delay, Range 3-31.

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79Row Refresh Cycle Time(tRFC)Row Refresh Cycle Time(tRFC)

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80Minimum Refresh Recovery Time, Range 15-255.Minimum Refresh Recovery Time, Range 15-255.

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81Write to Read Delay(tWTR)Write to Read Delay(tWTR)

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82Internal Write to Read Command Delay, Range 3-31.Internal Write to Read Command Delay, Range 3-31.

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83Active to Active Delay(tRRD)Active to Active Delay(tRRD)

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84Row Active to Row Active Delay, Range 4-15.Row Active to Row Active Delay, Range 4-15.

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85Read CAS# Precharege(tRTP)Read CAS# Precharege(tRTP)

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86Read to Precharge Delay, Range 4-15.Read to Precharge Delay, Range 4-15.

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87Four Active Window Delay(tFAW)Four Active Window Delay(tFAW)

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88Four Active Window Delay, Range 4-63.Four Active Window Delay, Range 4-63.

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89Row Cycle Time(tRC)Row Cycle Time(tRC)

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90Row Cycle Time, Range 15-75.Row Cycle Time, Range 15-75.

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91QPI FrequencyQPI Frequency

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92Memory FrequencyXung bộ nhớ

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93Memory Clock MultiplierMemory Clock Multiplier

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94Memory MultiplierMemory Multiplier

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95Performance Memory ProfilesPerformance Memory Profiles

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96The selection of Performance Memory Profiles which impacts memory sizing behavior.The selection of Performance Memory Profiles which impacts memory sizing behavior.

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97AutomaticAutomatic

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98ManualManual